Phase-locked loop (PLL) and delay-locked loop (DLL) circuits are common clock elements generally used for clock phase shifting or clock injection delay removal and embedded in programmable logic devices (PLDs) and other integrated circuits. DLL circuits typically require a smaller chip area to implement and often have a more straightforward layout design than PLL circuits. Accordingly, DLL circuits are often preferred over PLL circuits.
Unfortunately, DLL circuits can be more susceptible to clock jitter caused by PVT (i.e., process, voltage, temperature) changes than PLL circuits. As a result, output clock signals provided by DLL circuits may exhibit substantial PVT-induced jitter.
In addition, because DLL circuits typically cannot remove clock jitter from input clock signals, such jitter may inhibit DLL circuits from maintaining a consistent phase lock with input clock signals. When phase lock is lost, glitches and additional jitter may appear in the output clock signals provided by DLL circuits. As input clock signals are passed through delay cells of DLL circuits, the duty cycle of output clock signals provided by the DLL circuits can also degrade.
Accordingly, there is a need for an improved DLL circuit that is jitter tolerant and can reduce the possibility of clock glitches and duty cycle variance appearing in output clock signals.